News

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Creonic Adds oFEC Codec IP Core to Portfolio, Expanding High-Speed Networking Solutions for ASIC and FPGA
Creonic GmbH, a leading provider of ready-to-use IP cores for ASIC and FPGA applications, announces the release of its new oFEC (Open Forward Error Correction) codec IP core. The solution supports ...
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Expedera s Origin Evolution NPU IP Brings Generative AI to Edge Devices
Expedera launches its Origin Evolution NPU IP, bringing hardware acceleration to meet the computational demands of running ...
Design And Reuse9h
PolarFire Core devices streamline costs while retaining the market-leading power efficiency, security and reliability of classic PolarFire families
PolarFire Core devices are supported by Microchip’s Libero® SoC Design Suite, SmartHLS™ compiler, VectorBlox™ Accelerator SDK and Microchip’s Mi-V ecosystem of partner platforms for rapid RISC-V ...
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Boosting RISC-V SoC performance for AI and ML applications
At around the same time, the open and configurable RISC-V instruction set architecture (ISA) is experiencing rapid adoption across diverse markets. This growth aligns with rising SoC complexity and ...
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BrainChip CTO to Present on Architectural Innovation for Low-Power AI at the Embedded Vision Summit
Attendees of the Summit can visit BrainChip at booth #716 to see live demonstrations of the company’s latest advancements in Edge AI technology, including innovations in on-chip language processing, ...
Design And Reuse1d
sureCore extends its sureFIT design service to include custom memory solutions for AI applications
Sheffield, UK – 20 May 2025. SureCore, the leading memory specialist, has announced the expansion of its sureFIT design service to include AI applications, using its memory design expertise to help AI ...
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NVIDIA Unveils NVLink Fusion for Industry to Build Semi-Custom AI Infrastructure With NVIDIA Partner Ecosystem
COMPUTEX - May 19, 2025 — NVIDIA today unveiled NVIDIA NVLink Fusion™ — new silicon that lets industries build semi-custom AI infrastructure with the vast ecosystem of partners building with NVIDIA ...
Design And Reuse2d
Siemens to bring advanced timing constraint capabilities to EDA design flow with Excellicon acquisition
Acquisition enables System-on-a-Chip (SoC) designers to accelerate design closure and enhance functional and structural constraint correctness with industry-proven timing constraints management Plano, ...
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RISC-V Technology Seeing Growing Maturity and Penetration
An interesting data point presented by analyst Richard Wawrzyniak of the SHD Group highlighted the growing maturity and penetration of RISC-V technology: an expected flip from license-driven revenue ...
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Synopsys Interconnect IPs Enabling Scalable Compute Clusters
This strategic collaboration will leverage Synopsys' expertise in silicon IPs to assist in the development of bespoke AI silicon, forming the foundation for advanced compute clusters aimed at deliveri ...
Design And Reuse2d
Secure-IC at Computex 2025: Enabling Trust in AI, Chiplets, and Quantum-Ready Systems
In a landscape defined by AI acceleration , chiplet-based system integration, and upcoming post-quantum challenges, Secure-IC ...
Design And Reuse2d
InPsytech Joins Samsung SAFE™ IP Partner Program for Excellence in ONFI and UCIe IP Solutions
The Samsung SAFE™ program is designed to foster close collaboration between Samsung Foundry and its partners, encouraging innovation and efficiency across the semiconductor design ecosystem. By ...