Expedera launches its Origin Evolution NPU IP, bringing hardware acceleration to meet the computational demands of running ...

Creonic GmbH, a leading provider of ready-to-use IP cores for ASIC and FPGA applications, announces the release of its new oFEC (Open Forward Error Correction) codec IP core. The solution supports ...

Attendees of the Summit can visit BrainChip at booth #716 to see live demonstrations of the company’s latest advancements in Edge AI technology, including innovations in on-chip language processing, ...

PolarFire Core devices are supported by Microchip’s Libero® SoC Design Suite, SmartHLS™ compiler, VectorBlox™ Accelerator SDK and Microchip’s Mi-V ecosystem of partner platforms for rapid RISC-V ...

At around the same time, the open and configurable RISC-V instruction set architecture (ISA) is experiencing rapid adoption across diverse markets. This growth aligns with rising SoC complexity and ...

The Xilinx® LogiCORE™ 32G Fibre Channel (32GFC) RS-FEC IP core implements the Reed-Solomon Forward Error Correction (RS-FEC) sublayer as described in the INCITS ...

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January 27th, 2025 – T2M IP Technology proudly announces its partner’s latest innovations: next-generation 16-bit Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC) IP cores.

Grenoble July 16, 2024 -- Allegro DVT, the leading provider of video encoding and decoding semiconductor IP solutions, today announced the availability of its E320 video encoder IP which supports the ...

Hsinchu, Taiwan and San Jose, California, December 4 th, 2019 – Andes announces AndesCore™ 27-series CPU cores today and will present it at the RISC-V Summit. The 27-series is the first licensable ...