EDN

Targeting Floating-Point Algorithms for FPGA or ASIC Deployment

Native Floating-Point HDL code generation allows you to generate VHDL or Verilog for floating-point implementation in hardware without the effort of fixed-point conversion. Native Floating-Point HDL ...
EDN

How to achieve 1 trillion floating-point operations-per-second in an FPGA

Based on recent technological developments, high-performance floating-point signal processing can, for the very first time, be easily achieved using FPGAs. To date, virtually all FPGA-based signal ...
Design-Reuse

FPGA design and verification using Simulink

Xilinx System Generator for DSP is a MATLAB Simulink block set that facilitates system design. Targeting Xilinx FPGAs within the familiar MATLAB environment, System Generator for DSP gives you the ...
AOL

Avnet Electronics Marketing Americas Announces a New Development Kit Featuring MATLAB® and Simulink®

BOSTON & PHOENIX--(BUSINESS WIRE)-- Avnet Electronics Marketing Americas, a business region of Avnet, Inc. (NYSE: AVT), and MathWorks, the leading developer of mathematical computing software, today ...
Design-Reuse

Altera First to Benchmark Complex High-Performance Floating-Point Digital Signal Processing Designs on 28 nm FPGAs

Altera’s DSP Builder Advanced Blockset™ Design Flow Verified by BDTI, the Industry's Most Trusted Source of Independent DSP Technology Analysis San Jose, Calif., October 29, 2012— Altera ...